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powerpc 405cr embedded controller data sheet 1 features ibm powerpc tm 405 32-bit risc processor core operating up to 266mhz - memory management unit - 16kb instruction and 8kb data caches - multiply-accumulate (mac) function, including fast multiply unit - programmable timers - supports jtag for board level testing pc-100 synchronous dram (sdram) interface operating up to 133mhz - 32-bit interface for non-ecc applications - 40-bit interface serves 32 bits of data plus 8 check bits for ecc applications external peripheral bus - flash rom/boot rom interface - direct support for 8-, 16-, or 32-bit sram and external peripherals - up to eight devices - external mastering supported dma support for external peripherals, internal uart and memory - scatter-gather chaining supported - four channels programmable interrupt controller supports interrupts from a variety of sources - supports 7 external and 10 internal interrupts - edge triggered or level-sensitive - positive or negative active - non-critical or critical interrupt to processor core - programmable critical interrupt priority ordering - programmable critical interrupt vector for faster vector processing two serial ports (16550 compatible uart) one iic (i 2 c) interface general purpose i/o (gpio) available internal processor local bus (plb) runs at sdram interface frequency description the ibm powerpc 405cr tm is a 32-bit risc embedded controller. high performance, peripheral integration, and low cost make the device ideal for wired communications, network printers, and other computing applications. this device is an easy upgrade for systems based on powerpc 403xx embedded processors, while providing a base for custom chip designs. the controller is powered by a ppc405 embedded core. this core tightly couples a 266-mhz cpu, mmu, i- and d-cache, and debug logic. fine-tuning of the core reduces data transfer overhead, minimizes pipeline stalls, and greatly improves performance. the ppc405cr employs the ibm coreconnect tm bus architecture. this architecture, as implemented on the ppc405cr, consists of a 64-bit, 100-mhz processor local bus (plb) and a 32-bit, 50-mhz on-chip peripheral bus (opb).high-performance peripherals attach to the plb; and less performance-critical peripherals attach to the opb. technology: ibm cmos sa12e 0.25 m (0.18 m l eff ) package: 27mm, 316-ball enhanced plastic ball grid array (e-pbga) power (estimated): typical 0.9w, maximum 2.0w while the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made.
powerpc 405cr embedded controller data sheet 2 contents ordering and pvr information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 address map support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 sdram memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 external peripheral bus controller (ebc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 dma controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 iic bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 general purpose io (gpio) controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 universal interrupt controller (uic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 pin lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 spread spectrum clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figures ppc405cr embedded controller functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 27mm, 316-ball e-pbga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 input setup and hold waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 output delay and float timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
powerpc 405cr embedded controller data sheet 3 tables sysmem memory address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 dcr address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 signals listed alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 signals listed by ball assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 pin summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 signal functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 package thermal specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 recommended dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 sysclk and memclk timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 peripheral interface clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 i/o specifications?ll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 i/o specifications?00mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 i/o specifications?66mhz (preliminary) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 strapping pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
powerpc 405cr embedded controller data sheet 4 ordering and pvr information this section provides the part numbering nomenclature for the ppc405cr. for availability, contact your local ibm sales office. the part number contains a part modifier. this modifier provides for identification of future enhancements (for example, higher performance). each part number also contains a revision code. this refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only. the pvr (processor version register) is software accessible and contains additional information about the revision level of the part. refer to the ppc405cr user? manual for details on the register content. ibm part number key product name order part number 1 processor frequency package rev level pvr value jtag id ppc405cr IBM25PPC405CR-3BB200C 200mhz 27mm, 316 e-pbga b 0x40110041 0x22051049 ppc405cr IBM25PPC405CR-3BB200Cz 200mhz 27mm, 316 e-pbga b 0x40110041 0x22051049 ppc405cr ibm25ppc405cr-3bb266c 266mhz 27mm, 316 e-pbga b 0x40110041 0x22051049 ppc405cr ibm25ppc405cr-3bb266cz 266mhz 27mm, 316 e-pbga b 0x40110041 0x22051049 note 1: z at the end of the order part number indicates a tape and reel shipping package. otherwise, the chips are shipped in a tray. ibm part number IBM25PPC405CR-3BB200Cx package (e-pbga) processor speed grade 3 reliability case temperature range revision level shipping package* * blank = tray z = tape and reel (-40? to +85?)
powerpc 405cr embedded controller data sheet 5 ppc405cr embedded controller functional block diagram the ppc405cr is designed using the ibm microelectronics blue logic tm methodology in which major functional blocks are integrated together to create an application-speci? asic product. this approach provides a consistent way to create complex asics using ibm coreconnect tm bus architecture. note: ibm coreconnect busses provide: 64-bit plb interfaces up to 133mhz 32-bit opb interfaces up to 66mhz ppc405 processor core dcu icu dcr bus 16kb on-chip peripheral bus (opb) gpio iic uart uart dma bridge processor local bus (plb) sdram code decompression external bus controller controller clock control reset power mgmt jtag trace timers mmu controller opb interrupt controller arb - 32-bit addr - 32-bit data - 13-bit addr - 32-bit data external bus master controller universal i-cache 8kb d-cache (4-channel) (codepack ? ) dcrs * see peripheral interface clock timings table *serial clock 133mhz max 66mhz max
powerpc 405cr embedded controller data sheet 6 address map support the ppc405cr incorporates two simple and separate address maps. the first is a fixed processor address map that serves the powerpc family of processors. this address map defines the possible contents of various address regions which the processor can access. the second address map is for device configuration registers (dcr). this address map is accessed by software running on the ppc405cr processor through the use of mtdcr and mfdcr commands. sysmem memory address map 4gb system memory function sub function start address end address size local memory/peripherals 1 00000000 7fffffff 2gb reserved 80000000 ef5fffff internal peripherals total ef600000 efffffff 10mb uart0 ef600300 ef600307 8b reserved ef600308 ef6003ff uart1 ef600400 ef600407 8b reserved ef600408 ef6004ff iic0 ef600500 ef60051f 32b reserved ef600520 ef6005ff opb arbiter ef600600 ef60063f 64b reserved ef600640 ef6006ff gpio controller registers ef600700 ef60077f 128b reserved ef600780 efffffff expansion rom 2 f0000000 ffdfffff 254mb boot rom 2 ffe00000 ffffffff 2mb notes: 1. the local memory/peripheral area of the memory map can be configured for sdram, rom or peripherals. 2. the boot rom and expansion rom area of the memory map are intended for use by rom or flash-type devices. while locating volatile sdram and sram in this region is supported by the controller it is not recommended that these regions be used for this purpose.
powerpc 405cr embedded controller data sheet 7 dcr address map 4kb device configuration register function base address strap/parameter start address(0:9) end address(0:9) size dcr address space 1 000 3ff 1kw (4kb) 1 reserved 000 00f 16w memory controller registers [0:8] = 000001000 010 011 2w external bus controller registers [0:8] = 000001001 012 013 2w decompression controller registers [0:8] = 000001010 014 015 2w reserved 016 07f 106w plb registers [0:5] = 000100 080 08f 16w reserved 090 09f 16w opb bridge out registers [0:6] = 000110 0 0a0 0a7 8w reserved 0a8 0af 8w clock, control and reset parm=0x0b0 0b0 0b7 8w power management parm=0x0b8 0b8 0bf 8w interrupt controller parm=0x0c0 0c0 0cf 16w reserved 0d0 0ff 48w dma controller registers [0:3] = 0100 100 13f 64w reserved 140 3ff 704w notes: 1. dcr address space is addressable with up to 10 bits (1024 or 1k unique addresses). each unique address represents a single 32-bit (word) register, or 1 kiloword (kw) (which equals 4 kb).
powerpc 405cr embedded controller data sheet 8 sdram memory controller the ppc405cr memory controller core provides a low latency access path to sdram memory. a variety of system memory configurations are supported. the memory controller supports up to four logical banks. up to 256mb per bank are supported, up to a maximum of 1gb. memory timings, address and bank sizes, and memory addressing modes are programmable. features include: 11x8 to 13x11 addressing for sdram (2- and 4-bank) memory bus operates at same frequency as plb 32-bit memory interface support programmable address compare for each bank of memory - 4gb of address space industry standard 168-pin dimms are supported (some con?urations) up to 133mhz memory, includes pc133 support 4mb to 256mb per bank programmable address mapping and timing auto refresh page mode accesses with up to 4 open pages sync dram con?uration via mode set command power management (self-refresh) error checking and correction (ecc) support - standard sec/ded coverage - aligned nibble error detect - address error logging - mixed ecc/non-ecc banks - bypass mode external peripheral bus controller (ebc) up to eight rom, eprom, sram, flash, and slave peripheral i/o banks supported up to 50mhz operation burst and non-burst devices 8-, 16-, 32-bit byte-addressable data bus width support latch data on ready, synchronous or asynchronous
powerpc 405cr embedded controller data sheet 9 programmable 2k clock time-out counter with disable for ready programmable access timing per device - 256 wait states for non-burst - 32 burst wait states for ?st access and up to 8 wait states for subsequent accesses - programmable cson, csoff relative to address - programmable oeon, weon, weoff (1 to 4 clock cycles) relative to cs programmable address mapping peripheral device pacing with external ?eady external master interface - write posting from external master - read prefetching on plb for external master reads - bursting capable from external master - allows external master access to all non-ebc plb slaves - external master can control ebc slaves for own access and control dma controller supports the following transfers: - memory-to-memory transfers - buffered peripheral to memory transfers - buffered memory to peripheral transfers four channels scatter/gather capability for programming multiple dma operations 8-, 16-, 32-bit peripheral support (opb and external) 32-bit addressing address increment or decrement internal 32-byte data buffering capability supports internal and external peripherals support for memory mapped peripherals support for peripherals running on slower frequency buses
powerpc 405cr embedded controller data sheet 10 uart one 8-pin uart and one 4-pin uart interface provided selectable internal or external serial clock to allow wide range of baud rates register compatibility with ns16550 register set complete status reporting capability transmitter and receiver are each buffered with16-byte fifos when in fifo mode fully programmable serial-interface characteristics supports dma using internal dma engine iic bus interface compliant with phillips?semiconductors i 2 c speci?ation, dated 1995 operation at 100khz or 400khz 8-bit data 10- or 7-bit address slave transmitter and receiver master transmitter and receiver multiple bus masters supports ?ed v dd iic interface two independent 4 x 1 byte data buffers twelve memory-mapped, fully programmable con?uration registers one programmable interrupt request signal provides full management of all iic bus protocol programmable error recovery
powerpc 405cr embedded controller data sheet 11 general purpose io (gpio) controller controller functions and gpio registers are programmed and accessed via memory-mapped opb bus master accesses. all gpios are pin-shared with other functions. dcrs control whether a particular pin that has gpio capabilities acts as a gpio or is used for another purpose. twenty-three gpios are multiplexed with: - 7 of 8 chip selects - all seven external interrupts - all nine instruction trace pins each gpio output is separately programmable to emulate an open drain driver (i.e., drives to zero, three- stated if output bit is 1). universal interrupt controller (uic) the universal interrupt controller (uic) provides the control, status, and communications necessary between the various sources of interrupts and the local powerpc processor. features include: supports 7 external and 10 internal interrupts edge triggered or level-sensitive positive or negative active non-critical or critical interrupt to ppc405 processor core programmable critical interrupt priority ordering programmable critical interrupt vector for faster vector processing jtag ieee 1149.1 test access port ibm riscwatch debugger support jtag boundary scan description language (bsdl)
powerpc 405cr embedded controller data sheet 12 27mm, 316-ball e-pbga package m 1.27 typ 0.75 0.15 solderball x 316 27.0 24.13 27.0 b a c 0.20 ? 0.30 ? 0.15 c 27.0 ref reserved area for ejector pin mark x 4 typ corner shape is chamferred or rounded 0.20 c c 2.65 max 0.6 0.1 pcb substrate mold compound thermal balls top view bottom view 0.25 0.35 c c y w v u t r p n m l k j h g f e d c b a m a b 7.5 typ 15.0 typ gold gate release corresponds to a1 ball location 27.0 20 19 18 17 16 6 7 8 9 10 11 12 13 14 15 5 4 3 2 1 note: all dimensions are in mm.
powerpc 405cr embedded controller data sheet 13 signals listed alphabetically signal name ball interface group page av dd e20 power 29 ba0 ba1 j17 h18 sdram interface 24 banksel0 banksel1 banksel2 banksel3 l19 n17 p17 u19 sdram interface 24 busreq p2 external master peripheral interface 26 cas k17 sdram interface 24 clken0 clken1 j19 g20 sdram interface 24 dmaack0 dmaack1 dmaack2 dmaack3 c16 b17 b16 a14 external slave peripheral interface 24 dmareq0 dmareq1 dmareq2 dmareq3 a19 c15 b15 a8 external slave peripheral interface 24 dqm0 dqm1 dqm2 dqm3 u18 w14 y10 u8 sdram interface 24 dqmcb v19 sdram interface 24 drvrinh1 drvrinh2 f17 c19 system interface 28 ecc0 ecc1 ecc2 ecc3 ecc4 ecc5 ecc6 ecc7 v17 y18 u14 v13 y13 v12 w11 v11 sdram interface 24 eot0[tc0] eot1[tc1] eot2[tc2] eot3[tc3] g4 f2 w1 y2 external slave peripheral interface 24 extack extreq extreset u5 y3 p4 external master peripheral interface 26
powerpc 405cr embedded controller data sheet 14 gnd a1 a6 a10 a15 a20 b2 b19 c3 c18 d4 d17 e5 e10 e11 e16 f1 f20 j9 j10 j11 j12 k5 k9 k10 k11 k12 k16 k20 l1 l5 l9 l10 l11 l12 l16 m9 m10 m11 m12 r1 r20 power 29 signals listed alphabetically (continued) signal name ball interface group page
powerpc 405cr embedded controller data sheet 15 gnd (cont) t5 t10 t11 t16 u4 u17 v3 v18 w2 w19 y1 y6 y11 y15 y20 power 29 gpio1[ts1e] gpio2[ts2e] gpio3[ts1o] gpio4[ts2o] gpio5[ts3] gpio6[ts4] gpio7[ts5] gpio8[ts6] gpio9[trcclk] b18 d16 c17 p18 t17 w18 y19 w13 v6 system interface 28 halt e19 system interface 28 holdack holdpri holdreq t4 t3 v2 external master peripheral interface 26 iicscl u15 internal peripheral interface 26 iicsda w17 internal peripheral interface 26 irq0[gpio17] irq1[gpio18] irq2[gpio19] irq3[gpio20] irq4[gpio21] irq5[gpio22] irq6[gpio23] d18 c20 e18 d20 g17 f18 w20 interrupts interface 27 memaddr0 memaddr1 memaddr2 memaddr3 memaddr4 memaddr5 memaddr6 memaddr7 memaddr8 memaddr9 memaddr10 memaddr11 memaddr12 y7 w7 v8 u7 y4 u6 w4 v5 w3 v4 u3 v1 t2 sdram interface 24 signals listed alphabetically (continued) signal name ball interface group page
powerpc 405cr embedded controller data sheet 16 memclkout0 memclkout1 h20 g18 sdram interface 24 memdata0 memdata1 memdata2 memdata3 memdata4 memdata5 memdata6 memdata7 memdata8 memdata9 memdata10 memdata11 memdata12 memdata13 memdata14 memdata15 memdata16 memdata17 memdata18 memdata19 memdata20 memdata21 memdata22 memdata23 memdata24 memdata25 memdata26 memdata27 memdata28 memdata29 memdata30 memdata31 j18 k19 l20 m20 m19 l18 l17 n20 n19 m18 m17 p20 p19 n18 u20 t18 w16 y17 y16 v14 y14 u12 w12 y12 y9 w9 v10 u10 y8 w8 v9 u9 sdram interface notes: 1. memdata0 is the most significant bit (msb) 2. memdata31 is the least significant bit (lsb) 24 ov dd f5 g5 p5 r5 t6 t7 t14 t15 f16 g16 p16 r16 e6 e7 e14 e15 power 29 signals listed alphabetically (continued) signal name ball interface group page
powerpc 405cr embedded controller data sheet 17 peraddr0 peraddr1 peraddr2 peraddr3 peraddr4 peraddr5 peraddr6 peraddr7 peraddr8 peraddr9 peraddr10 peraddr11 peraddr12 peraddr13 peraddr14 peraddr15 peraddr16 peraddr17 peraddr18 peraddr19 peraddr20 peraddr21 peraddr22 peraddr23 peraddr24 peraddr25 peraddr26 peraddr27 peraddr28 peraddr29 peraddr30 peraddr31 a3 a4 b6 d7 c6 b7 d8 c7 b8 a7 d9 c8 b9 d10 c9 a9 b11 a11 b12 d11 a13 b13 c12 d12 b14 c13 d13 a16 c14 d14 a17 d15 external slave peripheral interface note: peraddr0 is the most significant bit (msb) on this bus. 24 perblast e2 external slave peripheral interface 24 perclk d3 external master peripheral interface 26 percs0 percs1 [gpio10] percs2 [gpio11] percs3 [gpio12] percs4 [gpio13] percs5 [gpio14] percs6 [gpio15] percs7 [gpio16] d6 b5 c5 a5 b10 c10 a12 c11 external slave peripheral interface 24 signals listed alphabetically (continued) signal name ball interface group page
powerpc 405cr embedded controller data sheet 18 perdata0 perdata1 perdata2 perdata3 perdata4 perdata5 perdata6 perdata7 perdata8 perdata9 perdata10 perdata11 perdata12 perdata13 perdata14 perdata15 perdata16 perdata17 perdata18 perdata19 perdata20 perdata21 perdata22 perdata23 perdata24 perdata25 perdata26 perdata27 perdata28 perdata29 perdata30 perdata31 u2 r4 u1 r2 r3 t1 n4 p3 n2 p1 m4 n3 m2 n1 l4 m3 l2 m1 k2 l3 k1 j1 j2 k3 k4 h1 h2 j3 j4 g1 g2 h3 external slave peripheral interface note: perdata0 is the most significant bit (msb) on this bus. 24 pererr b1 external master peripheral interface 26 peroe e4 external slave peripheral interface 24 perpar0 perpar1 perpar2 perpar3 c2 g3 e1 h4 external slave peripheral interface 24 perready e3 external slave peripheral interface 24 perr/w c1 external slave peripheral interface 24 perwbe0 perwbe1 perwbe2 perwbe3 perwe d2 f4 f3 d1 c4 external slave peripheral interface 24 ras k18 sdram interface 24 rcvrinh e17 system interface 28 signals listed alphabetically (continued) signal name ball interface group page
powerpc 405cr embedded controller data sheet 19 reserved g19 j20 r17 t20 v16 other pins note: g19 must be tied to ov dd or gnd. all other reserved pins should be left unconnected. 29 sysclk syserr sysreset h17 a18 d19 system interface 28 tck tdi tdo b4 a2 d5 jtag interface 27 testen f19 system interface 28 tmrclk b20 system interface 28 tms b3 jtag interface 27 trst h19 jtag interface 27 uart0_cts uart0_dcd uart0_dsr uart0_dtr uart0_ri uart0_rts uart0_rx uart0_tx w10 r18 u16 u13 v15 v20 t19 w15 internal peripheral interface 26 uart1_dsr [uart1_cts ] uart1 _ rts [u art1_dtr ] uart1_rx uart1_tx v7 w6 w5 y5 internal peripheral interface 26 uartserclk r19 internal peripheral interface 26 v dd e8 e9 e12 e13 h5 h16 j5 j16 m5 m16 n5 n16 t8 t9 t12 t13 power 29 we u11 sdram interface 24 signals listed alphabetically (continued) signal name ball interface group page
powerpc 405cr embedded controller data sheet 20 signals listed by ball assignment ball signal name ball signal name ball signal name ball signal name a1 gnd b10 percs4 [gpio13] c19 drvrinh2 e8 v dd a2 tdi b11 peraddr16 c20 irq1[gpio18] e9 v dd a3 peraddr0 b12 peraddr18 d1 perwbe3 e10 gnd a4 peraddr1 b13 peraddr21 d2 perwbe0 e11 gnd a5 percs3 [gpio12] b14 peraddr24 d3 perclk e12 v dd a6 gnd b15 dmareq2 d4 gnd e13 v dd a7 peraddr9 b16 dmaack2 d5 tdo e14 ov dd a8 dmareq3 b17 dmaack1 d6 percs0 e15 ov dd a9 peraddr15 b18 gpio1[ts1e] d7 peraddr3 e16 gnd a10 gnd b19 gnd d8 peraddr6 e17 rcrvinh a11 peraddr17 b20 tmrclk d9 peraddr10 e18 irq2[gpio19] a12 percs6 [gpio15] c1 perr/w d10 peraddr13 e19 syshalt a13 peraddr20 c2 perpar0 d11 peraddr19 e20 av dd a14 dmaack3 c3 gnd d12 peraddr23 f1 gnd a15 gnd c4 perwe d13 peradd26 f2 eot1(tc1) a16 peraddr27 c5 percs2 [gpio11] d14 peraddr29 f3 perwbe2 a17 peraddr30 c6 peraddr4 d15 peraddr31 f4 perwbe1 a18 syserr c7 peraddr7 d16 gpio2[ts2e] f5 ov dd a19 dmareq0 c8 peraddr11 d17 gnd f16 ov dd a20 gnd c9 peraddr14 d18 irq0[gpio17] f17 drvrinh1 b1 pererr c10 percs5 [gpio14] d19 sysreset f18 irq5[gpio22] b2 gnd c11 percs7 [gpio16] d20 irq3[gpio20] f19 testen b3 tms c12 peraddr22 e1 perpar2 f20 gnd b4 tck c13 peraddr25 e2 perblast g1 perdata29 b5 percs1 [gpio10] c14 peraddr28 e3 perready g2 perdata30 b6 peraddr2 c15 dmareq1 e4 peroe g3 perpar1 b7 peraddr5 c16 dmaack0 e5 gnd g4 eot0[tc0] b8 peraddr8 c17 gpio3[ts1o] e6 ov dd g5 ov dd b9 peraddr12 c18 gnd e7 ov dd g16 ov dd
powerpc 405cr embedded controller data sheet 21 g17 irq4[gpio21] k2 perdata18 m3 perdata15 p18 gpio4[ts2o] g18 memclkout1 k3 perdata23 m4 perdata10 p19 memdata12 g19 reserved k4 perdata24 m5 v dd p20 memdata11 g20 clken1 k5 gnd m9 thermal ball r1 gnd h1 perdata25 k9 thermal ball m10 thermal ball r2 perdata3 h2 perdata26 k10 thermal ball m11 thermal ball r3 perdata4 h3 perdata31 k11 thermal ball m12 thermal ball r4 perdata1 h4 perpar3 k12 thermal ball m16 v dd r5 ov dd h5 v dd k16 gnd m17 memdata10 r16 ov dd h16 v dd k17 cas m18 memdata9 r17 reserved h17 sysclk k18 ras m19 memdata4 r18 uart0_dcd h18 ba1 k19 memdata1 m20 memdata3 r19 uartserclk h19 trst k20 gnd n1 perdata13 r20 gnd h20 memclkout0 l1 gnd n2 perdata8 t1 perdata5 j1 perdata21 l2 perdata16 n3 perdata11 t2 memaddr12 j2 perdata22 l3 perdata19 n4 perdata6 t3 holdpri j3 perdata27 l4 perdata14 n5 v dd t4 holdack j4 perdata28 l5 gnd n16 v dd t5 gnd j5 v dd l9 thermal ball n17 banksel1 t6 ov dd j9 thermal ball l10 thermal ball n18 memdata13 t7 ov dd j10 thermal ball l11 thermal ball n19 memdata8 t8 v dd j11 thermal ball l12 thermal ball n20 memdata7 t9 v dd j12 thermal ball l16 gnd p1 perdata9 t10 gnd j16 v dd l17 memdata6 p2 busreq t11 gnd j17 ba0 l18 memdata5 p3 perdata7 t12 v dd j18 memdata0 l19 banksel0 p4 extreset t13 v dd j19 clken0 l20 memdata2 p5 ov dd t14 ov dd j20 reserved m1 perdata17 p16 ov dd t15 ov dd k1 perdata20 m2 perdata12 p17 banksel 2 t16 gnd signals listed by ball assignment (continued) ball signal name ball signal name ball signal name ball signal name
powerpc 405cr embedded controller data sheet 22 t17 gpio5 (ts3) u18 dqm0 v19 dqmfscb w20 irq6[gpio23] t18 memdata15 u19 banksel3 v20 uart0_rts y1 gnd t19 uart0_rx u20 memdata14 w1 eot2[tc2] y2 eot3[tc3] t20 reserved v1 memaddr11 w2 gnd y3 extreq u1 perdata2 v2 holdreq w3 memadd8 y4 memaddr4 u2 perdata0 v3 gnd w4 memadd6 y5 uart1_tx u3 memaddr10 v4 memaddr9 w5 uart1_rx y6 gnd u4 gnd v5 memaddr7 w6 uart1 _ rts [uart1_dtr ] y7 memaddr0 u5 extack v6 gpio9[trcclk] w7 memaddr1 y8 memdata28 u6 memaddr5 v7 uart1_dsr [uart1_cts ] w8 memdata29 y9 memdata24 u7 memaddr3 v8 memaddr2 w9 memdata25 y10 dqm2 u8 dqm3 v9 memdata30 w10 uart0_cts y11 gnd u9 memdata31 v10 memdata26 w11 ecc6 y12 memdata23 u10 memdata27 v11 ecc7 w12 memdata22 y13 ecc4 u11 we v12 ecc5 w13 gpio8[ts6] y14 memdata20 u12 memdata21 v13 ecc3 w14 dqm1 y15 gnd u13 uart0_dtr v14 memdata19 w15 uart0_tx y16 memdata14 u14 ecc2 v15 uart0_ri w16 memdata1 y17 memdata17 u15 iic_scl v16 reserved w17 iic_sda y18 ecc1 u16 uart0_dsr v17 ecc0 w18 gpio6[ts4] y19 gpio7[ts5] u17 gnd v18 gnd w19 gnd y20 gnd signals listed by ball assignment (continued) ball signal name ball signal name ball signal name ball signal name
powerpc 405cr embedded controller data sheet 23 pin lists the ppc405cr embedded controller is packaged in a 456-ball enhanced plastic ball grid array (e-pbga). the following tables describe the package level pinout. in the table ?ignal functional description?on page 24, each i/o signal is listed along with a short description of the signal function. some signals are multiplexed onto the same pin (ball) so that the pin is usable for different functions. multiplexed signals are shown in square brackets following the default signal (for example, c0:3[be0:3 ]) and described consecutively within each pin functional description. active-low signals such as be0:3 are marked with an overline. it is expected that in any single application a particular pin will always be programmed to serve the same function. the flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise be possible. in addition to multiplexing, many pins are also multi-purpose. these pins are described in the table using a single row with a text description that indicates the different functional uses of the pin. for example, the ebc peripheral controller address pins are used as outputs by the ppc405cr to broadcast an address to external slave devices when the ppc405cr has control of the external bus. when during the course of normal chip operation an external master gains ownership of the external bus, these same pins are used as inputs which are driven by the external master and received by the ebc in the ppc405cr. one group of pins is used as strapped inputs during system reset. these pins function as strapped inputs only during reset and are used for other functions during normal operation (see ?trapping?on page 39). note that these are not multiplexed pins since the function of the pins is not programmable. the following table lists all of the i/o signals provided by the ppc405cr. please refer to ?ignals listed alphabetically?on page 13 for the pin number to which each signal is assigned. pin summary group no. of pins sdram 71 external peripheral 97 external master 9 internal peripheral 15 interrupts 7 jtag 5 system 18 total signal pins 222 av dd 1 ov dd 16 v dd 16 gnd 40 thermal (and gnd) 16 reserved 5 total pins 316
powerpc 405cr embedded controller data sheet 24 signal functional description (part 1 of 6) multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k ? to 3.3v, 10k ? to 5v ) 3. must pull down (recommended value is 1k ? ) 4. if not used, must pull up (recommended value is 3k ? to 3.3v) 5. if not used, must pull down (recommended value is 1k ? ) 6. strapping input during reset; pull-up or pull-down required signal name description i/o type notes sdram interface memdata0:31 memory data bus notes: 1. memdata0 is the most significant bit (msb) 2. memdata31 is the least significant bit (lsb) i/o 3.3v lvttl 4 memaddr12:0 memory address bus o 3.3v lvttl ba0:1 bank address supporting up to four internal banks o 3.3v lvttl ras row address strobe o 3.3v lvttl cas column address strobe o 3.3v lvttl dqm0:3 dqm for byte lanes 0 (memdata0:7), 1 (memdata8:15), 2 (memdata16:23), and 3 (memdata24:31) o 3.3v lvttl dqmcb dqm for ecc check bits o 3.3v lvttl ecc0:7 ecc check bits 0:7 i/o 3.3v lvttl 4 banksel0 :3 select up to four external sdram banks o 3.3v lvttl we write enable o 3.3v lvttl clken0:1 sdram clock enable o 3.3v lvttl memclkout0:1 two copies of an sdram clock allows, in some cases, glueless sdram attach without requiring this signal to be repowered by a pll or zero-delay buffer. o 3.3v lvttl external slave peripheral interface perdata0:31 peripheral data bus used by ppc405cr when not in external master mode, otherwise used by external master note: perdata0 is the most significant bit (msb) on this bus. i/o 5v tolerant 3.3v lvttl 1 peraddr0:31 peripheral address bus used by ppc405cr when not in external master mode, otherwise used by external master. note: peraddr0 is the most significant bit (msb) on this bus. i/o 5v tolerant 3.3v lvttl 1 perpar0:3 peripheral byte parity signals i/o 5v tolerant 3.3v lvttl 1 perwbe0 :3 perwe as outputs, these pins can act as byte-enables which are valid for an entire cycle or as write-byte-enables which are valid for each byte on each data transfer, allowing partial word transactions. as outputs, pins are used by either peripheral controller or dma controller depending upon the type of transfer involved. used as inputs when external bus master owns the external interface i/o 5v tolerant 3.3v lvttl 1, 2 percs0 peripheral chip select bank 0 o 5v tolerant 3.3v lvttl 2
powerpc 405cr embedded controller data sheet 25 percs1 :7 [gpio10:16] seven additional peripheral chip selects or general purpose i/o - to access this function, software must toggle a dcr register bit. o[i/o] 5v tolerant 3.3v lvttl 1,2 peroe used by either peripheral controller or dma controller depending upon the type of transfer involved. when the ppc405cr is the bus master, it enables the selected sdrams to drive the bus. o 5v tolerant 3.3v lvttl 2 perr/w used by the ppc405cr when not in external master mode, as output by either the peripheral controller or dma controller depending upon the type of transfer involved. high indicates a read from memory, low indicates a write to memory. otherwise it used by the external master as an input to indicate the direction of transfer. i/o 5v tolerant 1, 2 perready used by a peripheral slave to indicate it is ready to transfer data. i 5v tolerant rcvr 1, 2 perblast used by the ppc405cr when not in external master mode, otherwise used by external master. indicates the last transfer of a memory access. i/o 5v tolerant 3.3v lvttl 1, 4 dmareq0:3 dmareq0:3 are used by slave peripherals to indicate they are prepared to transfer data. i 5v tolerant rcvr 1, 5 dmaack0:3 dmaack0:3 are used by the ppc405cr to indicate that data transfers have occurred. o 5v tolerant 3.3v lvttl 6 eot0:3[tc0:3] end of transfer/terminal count i/o 5v tolerant 3.3v lvttl 1, 5 signal functional description (part 2 of 6) multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k ? to 3.3v, 10k ? to 5v ) 3. must pull down (recommended value is 1k ? ) 4. if not used, must pull up (recommended value is 3k ? to 3.3v) 5. if not used, must pull down (recommended value is 1k ? ) 6. strapping input during reset; pull-up or pull-down required signal name description i/o type notes
powerpc 405cr embedded controller data sheet 26 external master peripheral interface perclk peripheral clock to be used by an external master and by synchronous peripheral slaves o 5v tolerant 3.3v lvttl extreset peripheral reset to be used by an external master and by synchronous peripheral slaves o 5v tolerant 3.3v lvttl holdreq hold request, used by an external master to request ownership of the peripheral bus i 5v tolerant rcvr 1, 5 holdack hold acknowledge, used by the ppc405cr to transfer ownership of peripheral bus to an external master o 5v tolerant 3.3v lvttl 6 extreq extreq is used by an external master to indicate it is prepared to transfer data i 5v tolerant rcvr 1, 4 extack extack is used by the ppc405cr to indicate that a data transfer occurred. o 5v tolerant 3.3v lvttl 6 holdpri used by an external master to indicate the priority of a given transfer (0 = high, 1 = low) i 5v tolerant rcvr 1, 4 busreq used when the ppc405cr needs to regain control of peripheral interface from an external master o 5v tolerant 3.3v lvttl pererr used as an input used to record external master errors and external slave peripheral errors i 5v tolerant rcvr 1, 5 internal peripheral interface uartserclk serial clock used to provide an alternative clock to the internally generated serial clock. used in cases where the allowable internally generated baud rates are not satisfactory. this input can be individually connected to either uart. i 5v tolerant 3.3v lvttl 1, 4 uart0_rx uart0 serial data in i 5v tolerant 3.3v lvttl 1, 4 uart0_tx uart0 serial data out o 5v tolerant 3.3v lvttl 6 uart0_dcd uart0 data carrier detect i 5v tolerant 3.3v lvttl 1, 4 uart0_dsr uart0 data set ready i 5v tolerant 3.3v lvttl 1, 4 uart0_cts uart0 clear to send i 5v tolerant 3.3v lvttl 1, 4 uart0_dtr uart0 data terminal ready o 5v tolerant 3.3v lvttl 6 uart0_rts uart0 request to send o 5v tolerant 3.3v lvttl 6 uart0_ri uart0 ring indicator i 5v tolerant 3.3v lvttl rcvr 1, 4 signal functional description (part 3 of 6) multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k ? to 3.3v, 10k ? to 5v ) 3. must pull down (recommended value is 1k ? ) 4. if not used, must pull up (recommended value is 3k ? to 3.3v) 5. if not used, must pull down (recommended value is 1k ? ) 6. strapping input during reset; pull-up or pull-down required signal name description i/o type notes
powerpc 405cr embedded controller data sheet 27 uart1_rx uart1 serial in data i 5v tolerant 3.3v lvttl rcvr 1, 4 uart1_tx uart1 serial out data. o 5v tolerant 3.3v lvttl 6 uart1_dsr [uart1_cts ] uart1 data set ready or uart1 clear to send. to access this function, software must toggle a dcr register bit. i 5v tolerant 3.3v lvttl rcvr 1, 4 uart1 _ rts [uart1_dtr ] uart1 request to send or uart1 data terminal ready. to access this function, software must toggle a dcr register bit. o 5v tolerant 3.3v lvttl 6 iicscl iic serial clock i/o 5v tolerant 3.3v lvttl 1, 2 iicsda iic serial data i/o 5v tolerant 3.3v lvttl 1, 2 interrupts interface irq0:6[gpio17:23] interrupt requests or general purpose i/o. to access this function, software must toggle a dcr register bit.] i[i/o] 5v tolerant 3.3v lvttl 1, 5 jtag interface tdi test data in i 5v tolerant 3.3v lvttl rcvr 1, 4 tms jtag test mode select i 5v tolerant 3.3v lvttl rcvr 1, 4 tdo test data out o 5v tolerant 3.3v lvttl tck jtag test clock i 5v tolerant 3.3v lvttl rcvr 1, 4 trst jtag reset i 5v tolerant rcvr 5 signal functional description (part 4 of 6) multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k ? to 3.3v, 10k ? to 5v ) 3. must pull down (recommended value is 1k ? ) 4. if not used, must pull up (recommended value is 3k ? to 3.3v) 5. if not used, must pull down (recommended value is 1k ? ) 6. strapping input during reset; pull-up or pull-down required signal name description i/o type notes
powerpc 405cr embedded controller data sheet 28 system interface sysclk main system clock input i 5v tolerant 3.3v lvttl rcvr sysreset main system reset. external logic can drive this bidirectional pin low (minimum of 16 cycles) to start a system reset. the ppc405cr then holds the output low for 8192 cycles to reset all internal and external logic connected to sysreset . a system reset can also be initiated by software. i/o 5v tolerant 3.3v lvttl rcvr 1, 2 syserr set to 1 when a machine check is generated. o 5v tolerant 3.3v lvttl halt halt from external debugger. i 5v tolerant 3.3v lvttl rcvr 1, 4 gpio1[ts1e] gpio2[ts2e] general purpose i/o or even trace execution status.to access this function, software must toggle a dcr register bit. i/o[o] 5v tolerant 3.3v lvttl 1, 6 gpio3[ts1o] gpio4[ts2o] general purpose i/o or odd trace execution status. to access this function, software must toggle a dcr register bit. i/o[o] 5v tolerant 3.3v lvttl 1 (a22, af18), 6 (af18 only) gpio5:8[ts3:6] general purpose i/o trace status. to access this function, software must toggle a dcr register bit. i/o[o] 5v tolerant 3.3v lvttl 1, 4 gpio9[trcclk]] general purpose i/o or trace interface clock. a toggling signal that is always half of the cpu core frequency. to access this function, software must toggle a dcr register bit. i/o[o] 5v tolerant 3.3v lvttl 1, 4 testen test enable i 5v tolerant rcvr w/ pd 3 rcvrinh receiver inhibit. set to 1 for normal operation. setting to 0 disables all inputs for test purposes. i 5v tolerant rcvr 2 drvrinh1:2 driver inhibit 1 and 2. set to 1 for normal operation. setting to 0 disables all outputs for test purposes. i 5v tolerant rcvr 2 tmrclk this input must toggle at a rate of less than one half the cpu core frequency (less than 100mhz in most cases). in most cases this input toggles much slower (in the 1mhz to 10mhz range). i 5v tolerant 3.3v lvttl rcvr 1, 4 signal functional description (part 5 of 6) multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k ? to 3.3v, 10k ? to 5v ) 3. must pull down (recommended value is 1k ? ) 4. if not used, must pull up (recommended value is 3k ? to 3.3v) 5. if not used, must pull down (recommended value is 1k ? ) 6. strapping input during reset; pull-up or pull-down required signal name description i/o type notes
powerpc 405cr embedded controller data sheet 29 power gnd ground note: pins j9?12, k9?12, l9?12, and m9?12 are also thermal balls. i av dd filtered voltage input for pll (analog) circuits i ov dd output driver voltage?.3v i v dd logic voltage?.5v i other pins reserved ex cept for g19, do not connect signals, voltage, or ground to these pins. g19 must be tied to ov dd or gnd. signal functional description (part 6 of 6) multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k ? to 3.3v, 10k ? to 5v ) 3. must pull down (recommended value is 1k ? ) 4. if not used, must pull up (recommended value is 3k ? to 3.3v) 5. if not used, must pull down (recommended value is 1k ? ) 6. strapping input during reset; pull-up or pull-down required signal name description i/o type notes
powerpc 405cr embedded controller data sheet 30 notes: 1. case temperature, t c , is measured at top center of case surface with device soldered to circuit board. 2. t a = t c ?p ca , where t a is ambient temperature and p is power consumption. 3. t cmax = t jmax ?p jc , where t jmax is maximum junction temperature and p is power consumption. 4. the above assumes that the chip is mounted on a card with at least one signal and two power planes. absolute maximum ratings the absolute maximum ratings below are stress ratings only. operation at or beyond these maximum ratings can cause permanent damage to the device characteristic symbol value unit supply voltage (internal logic) v dd 0 to 2.7 1 v supply voltage (i/o interface) ov dd 0 to 3.6 1 v pll supply voltage av dd 0 to 2.7 v input voltage (3.3v lvttl receivers) v in 0 to 3.6 v input voltage (5.0v lvttl receivers) v in 0 to 5.5 v storage temperature range t stg -55 to 150 c case temperature under bias t c -40 to +120 c notes: 1. if ov dd 0.4v it is required that v dd 0.4v. supply excursions not meeting this criteria must be limited to less than 25ms dura- tion during each power up or power down event. package thermal speci?ations the ppc405cr is designed to operate within a case temperature range of -40?c to 120?c. thermal resistance values for the e-pbga package in a convection environment are as follows: parameter symbol air?w ft/min (m/sec) unit 0 (0) 100 (0.51) 200 (1.02) junction-to-case thermal resistance jc 2 2 2 ?/w case-to-ambient thermal resistance (without heat sink) ca 18 16 15 ?/w
powerpc 405cr embedded controller data sheet 31 recommended dc operating conditions note: device operation beyond the conditions speci?d is not recommended. extended operation beyond the recom- mended conditions can affect device reliability. parameter symbol minimum typical maximum unit notes logic supply voltage v dd 2.3 2.5 2.7 v i/o supply voltage ov dd 3.0 3.3 3.6 v pll supply voltage av dd 2.3 2.5 2.7 v input logic high (3.3v lvttl receivers) v ih 2.0 ov dd v input logic high (5.0v lvttl receivers) v ih 2.0 5.5 v input logic low v il 0 0.8 v output logic high v oh 2.4 ov dd v output logic low v ol 0 0.4 v input leakage current (no pull-up or pull-down) i il1 00 a input leakage current for pull- down i il2 0 (lpdl) 400 (mpul) a input leakage current for pull-up i il3 ? 250 (lpdl) 0 (mpul) a input max allowable overshoot (3.3v lvttl receivers) v imao3 ov dd + 0.6 v input max allowable overshoot (5.0v lvttl receivers) v imao5 5.5 v input max allowable undershoot (3.3v or 5.0v receivers) v imau ? 0.6 v output max allowable overshoot (3.3v or 5.0v receivers) v omao ov dd + 0.3 v output max allowable undershoot (3.3v and 5.0v receivers) v omau3 ? 0.6 v case temperature t c ? 40 85 c capacitance parameter symbol maximum unit notes input capacitance group 1 (3.3v lvttl //o) c in1 2.5 pf input capacitance group 2 (5v tolerant lvttl i/o) c in2 3.5 pf input capacitance group 3 c in3 5.0 pf input capacitance group 1 (rx only pins) c in4 0.75 pf dc electrical characteristics parameter symbol minimum typical maximum unit active operating current (v dd )i dd tbd ma active operating current (ov dd )i odd tbd ma pll voltage v pll 2.3 2.5 2.7 v pll v dd input current i pll 16 23 ma
powerpc 405cr embedded controller data sheet 32 test conditions clock timing and switching characteristics are specified in accordance with operating conditions shown in the table ?ecommended dc operating conditions.?ac specifications are characterized at v dd = 3.14v and t j = 100?c with the 50pf test load (c l ) shown in the figure at right. timing waveform sysclk and memclk timing symbol parameter min max units sysclk input f c sysclk clock input frequency 25 66.6 mhz t c sysclk clock period 15 40 ns t cs clock edge stability 0.15 ns t ch clock input high time 40% of nominal period 60% of nominal period ns t cl clock input low time 40% of nominal period 60% of nominal period ns note: input slew rate > 2v/ns memclk output f c memclk clock output frequency?00mhz 100 mhz t c memclk clock period?00mhz 10 ns f c memclk clock output frequency?66mhz 133 mhz t c memclk clock period?66mhz 7.5 ns t ch clock output high time 35% of nominal period 65% of nominal period ns t cl clock output low time 35% of nominal period 65% of nominal period ns output pin c l c l = 50pf for all signals t cl t ch t c 2.0v 1.5v 0.8v
powerpc 405cr embedded controller data sheet 33 spread spectrum clocking care must be taken when using a spread spectrum clock generator (sscg) with the ppc405cr. this controller uses a pll for clock generation inside the chip. the accuracy with which the pll follows the sscg is referred to as tracking skew. the pll bandwidth and phase angle determine how much tracking skew there is between the sscg and the pll for a given frequency deviation and modulation frequency. when using an sscg with the ppc405cr the following conditions must be met: the frequency deviation must not violate the minimum clock cycle time. therefore, when operating the ppc405cr with one or more internal clocks at their maximum supported frequency, the sscg can only lower the frequency. the maximum frequency deviation cannot exceed ? 3%, and the modulation frequency cannot exceed 40khz. in some cases, on-board ppc405cr peripherals impose more stringent requirements (see note 1). use the peripheral bus clock for logic that is synchronous to the peripheral bus since this clock tracks the modulation. use the sdram memclk since it also tracks the modulation. notes: 1. the serial port baud rates are synchronous to the modulated clock. the serial port has a tolerance of approximately 1.5% on baud rate before framing errors begin to occur. the 1.5% tolerance assumes that the connected device is running at precise baud rates. 2. iic operation is unaffected. caution: it is up to the system designer to ensure that any sscg used with the ppc405cr meets the above requirements and does not adversely affect other aspects of the system.
powerpc 405cr embedded controller data sheet 34 peripheral interface clock timings parameter min max units perclk output frequency?00mhz (for external master or synchronous slaves) 50 mhz perclk period?00mhz 20 ns perclk output frequency?66mhz (for external master or synchronous slaves) 66 mhz perclk period?66mhz 15 ns perclk output high time 50% of nominal period 66% of nominal period ns perclk output low time 33% of nominal period 50% of nominal period ns uartserclk input frequency (note 1) 1000/(2t opb +2ns) mhz uartserclk period 2t opb +2 ?s uartserclk input high time t opb +1 ?s uartserclk input low time t opb +1 ?s tmrclk input frequency?00mhz 50 mhz tmrclk period?00mhz 20 ns tmrclk input frequency?66mhz 66 mhz tmrclk period?66mhz 15 ns tmrclk input high time 40% of nominal period 60% of nominal period ns tmrclk input low time 40% of nominal period 60% of nominal period ns notes: 1. t opb is the period in ns of the opb clock. the internal opb clock runs at 1/2 the frequency of the plb clock. the maximum opb clock frequency is 50 mhz for 200mhz parts and 66mhz.for 266mhz parts.
powerpc 405cr embedded controller data sheet 35 input setup and hold waveform output delay and float timing waveform 1.5v sysclk 1.5v t is t ih min min inputs valid data bus (inputs) d0:31 min min t ih t is 1.5v valid valid valid t ov t oh 1.5v min outputs sysclk outputs t of min max max 1.5v 1.5v
powerpc 405cr embedded controller data sheet 36 i/o speci?ations?ll signal input (ns) output (ns) output current (ma) clock notes setup time (minimum) hold time (minimum) valid delay (maximum) 50pf load hold time (minimum) 50pf load i/o h (maximum) i/o l (minimum) internal peripheral interface iicscl na na na na 19 12 iicsda na na na na 19 12 uart0_cts na na 12 8 uart0_dcd na na 12 8 uart0_dsr na na 12 8 uart0_dtr 12 8 uart0_ri na na 12 8 uart0_rts na na 12 8 uart0_rx na na 12 8 uart0_tx na na 12 8 uart1_rts [uart1_dtr] na na 12 8 uart1_dsr [uart1_cts] na na n/a n/a uart1_rx na na n/a n/a uart1_tx na na 12 8 uartserclk na na n/a n/a interrupts interface irq0:6[gpio17:23] 12 8 jtag interface tck n/a n/a async tdi n/a n/a async tdo 12 8 async tms n/a n/a async trst n/a n/a async system interface drvrinh1:2 dc dc n/a n/a n/a n/a gpio1[ts1e] gpio2[ts2e] gpio3[ts1o] gpio4[ts2o] gpio5[ts3] gpio6[ts4] gpio7[ts5] gpio8[ts6] gpio9[trcclk] 12 8 halt dc dc n/a n/a n/a n/a async rcvrinh dc dc n/a n/a n/a n/a sysclk n/a n/a n/a n/a syserr n/a n/a 12 8 async sysreset 12 8 async testen dc dc n/a n/a n/a n/a async tmrclk dc dc n/a n/a n/a n/a async
powerpc 405cr embedded controller data sheet 37 i/o speci?ations?00mhz notes: 1. the two-cycle sdram command interface is driven in cycle 1 and used in cycle 2. output times in table are in cycle 1. 2. sdram output timing is relative to the rising edge of the internal plb clock, which is an integral multiple of and rising- edge aligned with sysclk. therefore, sdram output timings in the table are shown relative to sysclk. timings shown are for a lumped 50pf load, however the interface has been verified for pc100-compliant operation using transmission line circuit analysis. 3. sdram clk0:1 rising edge at package pin precedes the internal plb clock by approximately 0.5ns for a typical clock network or a lumped 10pf load. 4. perclk rising edge at package pin with a 10pf load trails the internal plb clock by approximately 0.8ns. signal input (ns) output (ns) output current (ma) clock notes setup time (minimum) hold time (minimum) valid delay (maximum) 50pf load hold time (minimum) 50pf load i/o h (maximum) i/o l (minimum) sdram interface ba0:1 n/a n/a 7.3 1 19 12 sysclk 1, 2 banksel0:3 n/a n/a 5.8 1 19 12 sysclk 2 cas n/a n/a 7.3 1 19 12 sysclk 1, 2 clken0:1 n/a n/a 4.7 1 40 25 sysclk 2 dqm0:3 n/a n/a 6.2 1 19 12 sysclk 2 dqmcb n/a n/a 6 1 19 12 sysclk 2 ecc0:7 2 1 6 1 19 12 sysclk 2 memaddr12:0 n/a n/a 7.8 1 19 12 sysclk 1, 2 memclkout0:1 n/a n/a 0 -1 19 12 sysclk 2, 3 memdata0:31 2 1 6.2 1 19 12 sysclk 2 ras n/a n/a 7.4 1 19 12 sysclk 1, 2 we n/a n/a 7.4 1 19 12 sysclk 1, 2 external slave peripheral interface dmaack0:3 n/a n/a 8 0 12 8 perclk dmareq0:3 dc dc n/a n/a n/a n/a perclk eot0:3[tc0:3] dc dc 9 0 12 8 perclk peraddr0:31 4 1 10 0 19 12 perclk perblast 4 1 8 0 12 8 perclk percs0 percs1:7 [gpio10:16] n/a n/a 9 0 12 8 perclk perdata0:31 6 1 10 0 19 12 perclk peroe n/a n/a 8 0 12 8 perclk perpar0:3 4 1 10.5 0 19 12 perclk perr/w 5 1 8 0 12 8 perclk perready 9 1 n/a n/a n/a n/a perclk perwbe0:3 4 1 8 0 12 8 perclk external master peripheral interface busreq n/a n/a 8 0 12 8 perclk extack n/a n/a 8 0 12 8 perclk extreq 6 1 n/a n/a n/a n/a perclk extreset n/a n/a 8 0 19 12 perclk holdack n/a n/a 8 0 12 8 perclk holdpri 4 1 n/a n/a n/a n/a perclk holdreq 6 1 n/a n/a n/a n/a perclk perclk n/a n/a 0.9 0.9 19 12 plb clk 4 pererr 4 1 n/a n/a n/a n/a perclk
powerpc 405cr embedded controller data sheet 38 i/o speci?ations?66mhz (preliminary) notes: 1. the two-cycle sdram command interface is driven in cycle 1 and used in cycle 2. output times in table are in cycle 1. 2. sdram output timing is relative to the rising edge of the internal plb clock, which is an integral multiple of and rising- edge aligned with sysclk. therefore, sdram output timings in the table are shown relative to sysclk. timings shown are for a lumped 50pf load, however the interface has been verified for pc100-compliant operation using transmission line circuit analysis. 3. sdram clk0:1 rising edge at package pin precedes the internal plb clock by approximately 0.5ns for a typical clock network or a lumped 10pf load. 4. perclk rising edge at package pin with a 10pf load trails the internal plb clock by approximately 0.8ns. signal input (ns) output (ns) output current (ma) clock notes setup time (minimum) hold time (minimum) valid delay (maximum) 50pf load hold time (minimum) 50pf load i/o h (maximum) i/o l (minimum) sdram interface ba0:1 n/a n/a 5.5 1 19 12 sysclk 1, 2 banksel0:3 n/a n/a 4.5 1 19 12 sysclk 2 cas n/a n/a 5.5 1 19 12 sysclk 1, 2 clken0:1 n/a n/a 3.9 1 40 25 sysclk 2 dqm0:3 n/a n/a 4.9 1 19 12 sysclk 2 dqmcb n/a n/a 4.7 1 19 12 sysclk 2 ecc0:7 1.5 1 4.7 1 19 12 sysclk 2 memaddr12:0 n/a n/a 5.9 1 19 12 sysclk 1, 2 memclkout0:1 n/a n/a 0 1 19 12 sysclk 2, 3 memdata0:31 1.5 1 4.8 1 19 12 sysclk 2 ras n/a n/a 5.6 1 19 12 sysclk 1, 2 we n/a n/a 5.6 1 19 12 sysclk 1, 2 external slave peripheral interface dmaack0:3 n/a n/a 6 0 12 8 perclk dmareq0:3 dc dc n/a n/a n/a n/a perclk eot0:3[tc0:3] dc dc 8 0 12 8 perclk peraddr0:31 3 1 8 0 19 12 perclk perblast 3.5 1 6 0 12 8 perclk percs0 percs1:7 [gpio10:16] n/a n/a 6 0 12 8 perclk perdata0:31 5 1 8 0 19 12 perclk peroe n/a n/a 6 0 12 8 perclk perpar0:3 3.5 1 8 0 19 12 perclk perr/w 4 1 6 0 12 8 perclk perready 6.5 1 n/a n/a n/a n/a perclk perwbe0:3 3 1 6 0 12 8 perclk external master peripheral interface busreq n/a n/a 6 0 12 8 perclk extack n/a n/a 6 0 12 8 perclk extreq 5 1 n/a n/a n/a n/a perclk extreset n/a n/a 6 0 19 12 perclk holdack n/a n/a 6 0 12 8 perclk holdpri 3 1 n/a n/a n/a n/a perclk holdreq 5 1 n/a n/a n/a n/a perclk perclk n/a n/a 0.9 0.9 12 12 plb clk 4 pererr 3 1 n/a n/a n/a n/a perclk
powerpc 405cr embedded controller data sheet 39 strapping while the sysreset input pin is low (system reset), the state of certain i/o pins is read to enable default initial conditions prior to ppc405cr start-up. the actual capture instant is the nearest reference clock edge before the deassertion of reset. these pins must be strapped using external pull-up (logical 1) or pull-down (logical 0) resistors to select the desired default conditions. these pins are use for strap functions only during reset. they are used for other signals during normal operation. the following table lists the strapping pins along with their functions and strapping options: strapping pin assignments function option ball strapping pll tuning for 6 m 7 use choice 3 for 7 < m 12 use choice 5 for 12 < m 32 use choice 6 see note. w15 u13 v20 choice 1; tune[5:0] = 010001 0 0 0 choice 2; tune[5:0] = 010010 0 0 1 choice 3; tune[5:0] = 010011 0 1 0 choice 4; tune[5:0] = 010100 0 1 1 choice 5; tune[5:0] = 010101 1 0 0 choice 6; tune[5:0] = 010110 1 0 1 choice 7; tune[5:0] = 010111 1 1 0 choice 8; tune[5:0] = 100100 1 1 1 pll forward divider c16 b17 bypass mode 0 0 divide by 3 0 1 divide by 4 1 0 divide by 6 1 1 pll feedback divider b16 a14 divide by 1 0 0 divide by 2 0 1 divide by 3 1 0 divide by 4 1 1 plb divider from cpu b18 d16 divide by 1 0 0 divide by 2 0 1 divide by 3 1 0 divide by 4 1 1 opb divider from plb t4 u5 divide by 1 0 0 divide by 2 0 1 divide by 3 1 0 divide by 4 1 1 external bus divider from plb c17 p18 divide by 2 0 0 divide by 3 0 1 divide by 4 1 0 divide by 5 1 1
powerpc 405cr embedded controller data sheet 40 rom width y5 w6 8-bit rom 0 0 16-bit rom 0 1 32-bit rom 1 0 reserved 1 1 note: the tune bits adjust parameters that control pll jitter. the recommended values minimize jitter for the pll implemented in the ppc405cr. these bits are shown for information only; and do not require modi?ation except in special clocking circumstances such as spread spectrum clocking. for details on the use of spread spectrum clock generators (sscgs) with the ppc405cr, visit the technical documents area of the ibm powerpc web site. strapping pin assignments (continued) function option ball strapping
powerpc 405cr embedded controller data sheet 41 inside of back cover
powerpc 405cr embedded controller data sheet 42 (c) copyright international business machines corporation 1999, 2000 all rights reserved printed in the united states of america august 2000 the following are trademarks of international business machines corporation in the united states, or other countries, or both: other company, product, and service names may be trademarks or service marks of others. while the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made. all information contained in this document is subject to change without notice. the products described in this document are not intended for use in implantation or other life support applications where malfunction may result in injury or death to persons. the information contained in this document does not affect or change ibm product specifications or warranties. nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of ibm or third parties. all information contained in this document was obtained in specific environments, and is presented as an illustration. the results obtained in other operating environments may vary. the information contained in this document is provided on an "as is" basis. in no event will ibm be liable for damages arising directly or indirectly from any use of the information contained in this document. ibm microelectronics division 1580 route 52, bldg. 504 hopewell junction, ny 12533-6351 the ibm home page can be found at http://www.ibm.com the ibm microelectronics division home page can be found at http://www.chips.ibm.com sa14-2522-02 blue logic ibm powerpc 405cr codepack ibm logo coreconnect powerpc

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